Japanese Patent Published Application No. Hei 08-30549 discloses a conventional bus controller which performs bus arbitration among a plurality of bus masters M1 to M7 connected to a shared bus. When the bus masters M1 to M6 other than the bus master M7 having the highest priority output bus use requests, the bus arbitration circuit of this bus controller grants the ownership of the shared bus to a bus master which has the highest priority among the bus masters requesting the use of the shared bus. Also, when the bus master M7 having the highest priority outputs a bus use request while any one of the bus masters M1 to M6 is using the shared bus, a bus usage interruption judgment circuit judges whether or not the remaining bus cycle time, through which the bus master is to continue using the bus, exceeds a predetermined period. If the remaining bus cycle time does not exceed the predetermined period, the bus usage interruption judgment circuit permits the continued use of the bus as it is (in order not to deteriorate the overall system performance), and conversely if the remaining bus cycle time exceeds the predetermined period, the bus usage interruption judgment circuit interrupts the use of the bus by the bus master and grants the ownership of the bus to the bus master M7 having the highest priority (preferentially proceeding with the process of the bus master M7 having the highest priority).
Next, in an exemplary case where bus ownership is granted to the bus master M2, the operation of the bus master M2 will be explained in detail after bus ownership is granted. The bus master M2 outputs a memory address together with the number of the bus cycles required for data transmission and then starts the data transmission. On the other hand, the bus usage interruption judgment circuit detects the information of the number of the bus cycles as output from the bus master M2, and sets a cycle counter to the number. Then, the cycle counter counts down by one every time when the data transmission proceeds corresponding to one bus cycle.
By this process, if the bus master M7 having the highest priority outputs a bus use request to the bus usage interruption judgment circuit while the bus master M2 is transferring data, the bus usage interruption judgment circuit compares the value of the cycle counter to a maximum acceptable count. As a result, if the value of the cycle counter is less than the maximum acceptable count, the bus master M2 is permitted to continue the data transfer without taking any particular step.
However, if the value of the cycle counter equals or exceeds the maximum acceptable count, the bus usage interruption judgment circuit halts the bus master M2 transferring data, outputs a hold signal to the bus arbitration circuit and then grants bus ownership to the bus master M7 having the highest priority.
After receiving the hold signal from the bus usage interruption judgment circuit, the bus arbitration circuit does not perform bus arbitration anew while maintaining the state taken just before the hold signal is output from the bus usage interruption judgment circuit and, when the hold signal is removed, bus ownership is granted again to the bus master M2.
By this means, it is realized to maintain the overall system performance and preferentially proceed with the process of the bus master M7 having the highest priority.
However, once bus ownership is granted, the bus masters M1 to M6 can occupy the shared bus for the bus cycles as required unless the bus master M7 having the highest priority outputs a bus use request. Also, even if the bus master M7 having the highest priority outputs a bus use request during data transfer, the bus masters M1 to M6 can occupy the shared bus for the bus cycles as required in total only with a temporary halt. In the same manner, the bus master M7 having the highest priority and granted bus ownership can occupy the shared bus for the bus cycles as required. The number of clocks per bus cycle is fixed throughout the memory space in this case. Because of this, in the case where the common bus is connected to a plurality of different types of memory devices having different access speeds, superfluous clocks are inevitable in part of bus cycles.
Accordingly, there is a problem that the bus masters M1 to M6 other than the bus master M7 having the highest priority tend to wait for a substantial time so that the processing performance as viewed from the overall system tends to decrease. Particularly, this problem becomes significant when the throughput of data transfer is improved by the use of a fast access mode such as a page mode. In other words, because such a fast access mode is performed by successively transferring a certain amount of data to increase the throughput of the data transfer, the waiting time of the bus masters M1 to M6 tends to increase by this fast access mode.